1. Field
The following description relates to instruction processing, and more particularly, to processing of instructions to be executed by a very long instruction word (VLIW) processor.
2. Description of the Related Art
A very long instruction word (VLIW) processor includes a plurality of functional units which execute a plurality of instructions in parallel. A VLIW processor may be employed in a computer to reduce the time required to execute input instructions by distributing the input instructions among the plurality of functional units. For a software program to be executed by a VLIW processor, a plurality of instructions of the software program must be converted into one long instruction.
A compiler, which compiles an instruction word to be executed by a VLIW processor, tries to minimize the time required to execute a program by achieving optimum parallelism in the processor. However, instruction parallelism is limited by data dependency, control dependency due to branch instructions, resource conflicts, and the like. In particular, a branch instruction is a major limiting factor. In the case of a conditional branch instruction, the processing of the instruction is delayed while a condition is evaluated, thereby making continuous pipeline processing difficult because the next stage of the pipeline must wait until the delay is over.
Researches have been conducted to determine methods that overcome the performance limitations caused by branch instructions. One method suggested is predicated execution. In predicated execution, a compiler compiles an instruction word such that a conditionally executed instruction may be executed without using a branch instruction. For example, a determination may be made as to whether to execute an instruction based on a condition, and the branch instruction may be removed. For example, in predicated execution, if a condition is true, an instruction may be executed. If the condition is false, the instruction may not be executed. However, to support predicated execution, all instruction codes including non-predicated instructions must be generated as predicated instructions.